Title:

VHDL Seminar

Code:IVH
Ac.Year:2017/2018
Term:Summer
Curriculums:
ProgrammeBranchYearDuty
IT-BC-3BIT1stCompulsory-Elective - group T
IT-BC-3BIT2ndCompulsory-Elective - group T
Language:Czech
Private info:http://www.fit.vutbr.cz/study/courses/IVH/private/
Credits:4
Completion:accreditation
Type of
instruction:
Hour/semLecturesSem. ExercisesLab. exercisesComp. exercisesOther
Hours:0260013
 ExaminationTestsExercisesLaboratoriesOther
Points:0000100
Guarantee:Vašíček Zdeněk, doc. Ing., Ph.D., DCSY
Instructor:Vašíček Zdeněk, doc. Ing., Ph.D., DCSY
Faculty:Faculty of Information Technology BUT
Department:Department of Computer Systems FIT BUT
Follow-ups:
Design of Computer Systems (INP), DCSY
Digital Systems Design (INC), DCSY
Schedule:
DayLessonWeekRoomStartEndLect.Gr.St.G.EndG.
WedlecturelecturesD020612:0013:501BIAxxxx
WedlecturelecturesD020612:0013:501BIBxxxx
WedlecturelecturesD020612:0013:502BIAxxxx
WedlecturelecturesD020612:0013:502BIBxxxx
WedlecturelecturesD020612:0013:503BITxxxx
 
Learning objectives:
  To give the students the knowledge of syntax and semantics of hardware description language VHDL, its use for modelling, simulation, and synthesis of complex digital systems, as well as the skills in VHDL programming techniques and the use of professional design tools.
Description:
  Basic VHDL language constructs, lexical description, VHDL source code. Data types, data objects, data classes, data objects declaration. VHDL language commands. Advanced VHDL features, VHDL 93. Delay modelling, time scheduling in VHDL. Combinational circuits modelling, "don't cares", tri-state-output circuits. Sequential circuits modelling, Mealy and Moore automata. Models testing, test benches. Designing at algorithm, register-transfer, and gate levels. Modelling for synthesis. Semantics for simulation and synthesis, delay in model. Programming techniques, shared components, flattening and structuring. Case studies of complex digital circuits: UART, RISC processor, FIR filter.
Knowledge and skills required for the course:
  Basic skills in programming and digital design, fundamentals of Boolean algebra.
Learning outcomes and competences:
  The student should be able to describe and simulate complex digital systems using VHLD language constructs including both behavioral and structural description.
Syllabus of lectures:
 
  1. Moderní návrh hardware (design flow), jazyky pro popis hardware (VHDL, Verilog), FPGA, úvod do číslicových systémů.
  2. Základní konstrukce jazyka VHDL, lexikální popis, zdrojový text ve VHDL.
  3. Datové typy, datové objekty, třídy objektů, deklarace datových objektů.
  4. Příkazy jazyka VHDL
  5. Pokročilé vlastnosti jazyka VHDL, zpoždění a plánování času.
  6. Popis kombinačních obvodů, třístavové obvody.
  7. Popis synchronních sekvenčních obvodů, popis konečných automatů, asynchronní sekvenční obvody.
  8. Modelování obvodů a událostně řízená simulace, testování obvodů a návrh testů, funkční simulace (ModelSIM), co-simulace.
  9. Syntéza obvodů, omezení (constraints), syntéza pro FPGA, časová simulace.
  10. Pokročilé techniky (pipelining, retiming, sdílení komponent, flattening a strukturování)
  11. Příkladová studie komplexních obvodů: řízení maticového LED displeje, UART, ETHERNET
  12. Příkladová studie komplexních obvodů: RISC procesor
  13. Obvody FPGA, využití masivního paralelismu v kryptografii (RC4, DES), DNA-alignment
Syllabus - others, projects and individual work of students:
 Individual project.
Fundamental literature:
 
  • Chang, K.C.: Digital Design and Modeling with VHDL and Synthesis, IEEE Computer Society Press, 1997
  • Armstrong, J.R. - Gray F.G.: Structured Logic Design with VHDL, Prentice-Hall, 1993
  • Armstrong, J.R. - Gray, F.G.: VHDL Design Representation and Synthesis, 2nd edition, Prentice Hall, ISBN 0-13-021670-4, 2000
Study literature:
 
  • Lecture notes.
Progress assessment:
  Project and its defence supported by the written technical report in English language.
Exam prerequisites:
  Class credit is based on the successful project defence.