Publication Details

Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems

CHARVÁT Lukáš, SMRČKA Aleš and VOJNAR Tomáš. Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems. In: Proceedings of the 15th International Conference on Computer Aided Systems Theory (EUROCAST 2015). Las Palmas de Grand Canaria: The Universidad de Las Palmas de Gran Canaria, 2015, pp. 193-194. ISBN 978-84-606-5438-4.
Czech title
Analýza hazardů v mikroprocesorech pomocí formální analýzy parametrizovaných systémů
Type
conference paper
Language
english
Authors
Keywords

microprocessor analysis, pipelined execution, WAW hazard, WAR hazard, formal verification, parameterized systems

Abstract

Implementation of pipeline-based execution of instructions in purpose-specific microprocessors is an error prone task, which implies a need of proper verification of the resulting designs. Our long-term goal is to develop a set of verification techniques with formal roots, each of them specialised in checking absence of a certain kind of errors in purpose-specific microprocessors. The main idea is that, this way, a high degree of automation and scalability can be achieved since only parts of a design related to a specific error are to be investigated. In our previous works, we proposed, with the above goal in mind, fully automated approaches for checking correctness of the implementation of individual instructions and for verifying absence of read-after-write (RAW) hazards. In this paper, we extend our approach by aiming at write-after-write (WAW) and write-after-read (WAR) in microprocessors with a single pipeline.

Annotation
Implementation of pipeline-based execution of instructions in purpose-specific microprocessors is an error prone task, which implies a need of proper verification of the resulting designs. Our long-term goal is to develop a set of verification techniques with formal roots, each of them specialised in checking absence of a certain kind of errors in purpose-specific microprocessors. The main idea is that, this way, a high degree of automation and scalability can be achieved since only parts of a design related to a specific error are to be investigated. In our previous works, we proposed, with the above goal in mind, fully automated approaches for checking correctness of the implementation of individual instructions and for verifying absence of read-after-write (RAW) hazards. In this paper, we extend our approach by aiming at write-after-write (WAW) and write-after-read (WAR) in microprocessors with a single pipeline.
Published
2015
Pages
193-194
Proceedings
Proceedings of the 15th International Conference on Computer Aided Systems Theory (EUROCAST 2015)
Conference
Fifteenth International Conference on Computer Aided Systems Theory , Las Palmas de Gran Canaria, ES
ISBN
978-84-606-5438-4
Publisher
The Universidad de Las Palmas de Gran Canaria
Place
Las Palmas de Grand Canaria, ES
BibTeX
@INPROCEEDINGS{FITPUB10767,
   author = "Luk\'{a}\v{s} Charv\'{a}t and Ale\v{s} Smr\v{c}ka and Tom\'{a}\v{s} Vojnar",
   title = "Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems",
   pages = "193--194",
   booktitle = "Proceedings of the 15th International Conference on Computer Aided Systems Theory (EUROCAST 2015)",
   year = 2015,
   location = "Las Palmas de Grand Canaria, ES",
   publisher = "The Universidad de Las Palmas de Gran Canaria",
   ISBN = "978-84-606-5438-4",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/10767"
}
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